PU6812S2

Description: PU6812x2/61x2/62x2 series is a high performance motor driver dedicated chip integrated with 8051 kernel and motor control engine (ME). 8051 kernel deals with routine affairs, ME deals with motor real-timetransactions, and dual-core collaborative work realizes various high performance motor control. Most of the 8051 kernel instruction cycle is 1T or 2T, chip internal integration of high-speed operational amplifier, comparator, high-speed ADC, multiplier, divider, CRC, SPI, I2C, UART, a variety of TIMER, PWM and other functions, built-in high voltage LDO, BLDC/PMSM motor square wave, SVPWM/SPWM, FOC driver control.For the differences between PU6812 and PU6861, please refer to the Driver chapter. The output method of PU6812 is PWM, while the output of PU6861 is 6N Predriver.PU6812 package types:
PU6812L2 (LQFP48), PU6812N2 (QFN32), PU6812S2 (SSOP24), PU6812P2(LQFP32), PU6812V(SSOP24).
PU6861 package types: PU6861Q2 (QFN56), PU6861N2 (QFN40), PU6861L2(LQFP48).
PU6862 package types: PU6862L(LQFP48)、PU6862Q(QFN48).
For the convenience of description and differentiation, if specific packages are specified later, it means that this feature is exclusive to corresponding packages; otherwise, it is a common feature of PU6812x2/61x2/62x2 series chips.

Features: Power supply:
PU6812L2:
Supply HV Mode (VCC_MODE=0): VCC= 5~24V
Dual Supply Mode (VCC_MODE=1), VCC≥VDD5: VCC= 5~36V, VDD5=5V
Single Supply LV Mode (VCC_MODE=1): VCC=VDD5= 3~ 5.5V
PU6812N2/S2/P2/V:
Single Supply HV Mode: VCC= 5~24V
Single Supply LV Mode: VCC=VDD5= 3~ 5.5V
PU6812N2/S2/P2/V:
Single Supply HV Mode: VCC= 12~20V
PU6861Q2:
Mode 1: VCC_MODE=0, VCC= 5~24V, VDRV=7~18V
Mode 2: VCC_MODE=1, VCC=VDD5=3~5.5V, VDRV=7~18V
PU6861N2/NF2/L2:
Mode 1: VCC=5~24V, VDRV=7~18V
 Dual core: Motor engine ME and 8051 core. ME realize FOC/BLDC control automatically by hardware;
8051 core is used in parameter configuration and daily transaction processing
 Instruction cycles are mostly 1T or 2T.
 16KB Flash ROM, with CRC verification, support self-write and code protection
 256 bytes IRAM, 768 bytes XRAM
 ME: Integrated LPF, proportional integrator (PI), BLDC module, FOC module
 1T 16 x16 multiplier, 16T 32/16 divider
 4 priority level interrupt, 15 interrupt sources
 GPIO:
PU6812L2: 34 GPIO
PU6812N2: 20 GPIO
PU6812S2: 12 GPIO
PU6861Q2: 32 GPIO
PU6861N2: 19 GPIO
PU6861NF2: 19 GPIO
PU6861L2: 27 GPIO
PU6812P2: 21 GPIO
PU6812V: 13 GPIO
PU6862L: 20 GPIO
PU6862Q: 20 GPIO
 Timer:
2 universal programmable capture timers
1 support QEP decoding programmable timer
1 BLDC motor dedicated timer
1 general purpose timer
1 RTC timer
 I2C/SPI/UART interface with DMA support
 Analog peripheral:
12-bit ADC, 0.9us conversion time, select internal VREF, external VREF for reference voltage
Number of ADC channels:
PU6812L2: 12 channels
PU6861Q2: 12 channels
PU6812N2: 7 channels
PU6812S2: 5 channels
PU6861N2: 9 channels
PU6861NF2: 9 channels
PU6861L2: 11 channels
PU6812P2: 9 channels
PU6812V: 7 channels
PU6862L: 8 channels
PU6862Q: 8 channels
Built-in VREF reference for configureable 3V, 4V, 4.5V, VDD5 (PU6812S2/P2/V can only choose VDD5
for internal reference.
Built-in VHALF (1/2 VREF) reference output.
3 independent operational amplifiers (PU6812N2/S2 and PU6861N2 only have an independent op amp)
3-channel analog comparator
9-bit DAC
 Driver type:
PWM output (for PU6812L2/N2/S2/P/V)
6N Predriver (for PU6861Q2/N2/NF2/L2、PU6862L/Q)
 BLDC control supports automatic commutation, wave-by-wave current limiting, support for HALL、
BEMF position detection.
 FOC driver supports single/dual/three resistors current sampling (PU6812N2/S2 and PU6861N2 only
support single resistor current sampling).
 FOC driver supports overmodulation
 Built-in oscillator:
24MHz ± 2% high speed oscillator
32.8kHz low speed oscillator
 Watchdog Time
 Two-wire FICE protocol for on chip debugging

Package: SSOP24

Datasheet: -