PU6332N
- Description
- The high-performance motor drive chip incorporates ME core and 8051 core. ME core integrates FOC,
MDU, LPF, PID and SVPWM modules that allow for automatic calculation of FOC or square-wave control
by the hardware for sensored/sensorless BLDC motors. 8051 core is used for parameter configuration and
routine processing. Most of 8051 core instruction cycle takes 1T or 2T clock cycle(s). The dual cores work in
parallel to achieve high-performance motor control. The chip integrates high-speed operational amplifiers,
comparators, pre-driver, high-speed ADC, CRC, SPI, I2C, UART, LIN, Timers, built-in high-voltage LDO,
which are suitable for FOC or square-wave based BLDC motors
- Features
-
◼ Power supply:
➢ PU6332N
◆ High-voltage single-power supply mode: When VCC_MODE = 0, external power supply
5V~28V is connected to VCC pin and internal LDO supplies VDD5 voltage.
◆ Low-voltage single-power supply mode: When VCC_MODE = 1, external power supply
3V~5.5V is connected to VDD5 pin and VDD5 pin is shorted to VCC pin.
◆ Dual power supply mode: When VCC_MODE = 1, external power supply 1 (5V ~ 36V) is
connected to VCC pin and external power supply 2 (5V) is connected to VDD5 pin.
◼ Dual-core: 8051 core and ME core
◼ Magnetoresistance sensor with 180°degree angle measurement to sense magnetic field on X-Y plane
◼ An instruction cycle mostly takes 1 or 2 system clock cycle(s)
◼ 16kB Flash ROM with CRC, self-program and code protection
◼ 256 bytes IRAM and 768 bytes XRAM
◼ ME: Core integrating PID, FOC, MDU and LPF modules
◼ 16 interrupt sources that are configurable with 4 priority levels
◼ GPIO:
➢ PU6332N: 22 GPIOs
◼ Timers:
➢ Timer1: Timer designed for square-wave motor drive, supporting square-wave drive timing
control, automatic commutation and cycle-by-cycle current limiting
➢ Timer2: Timer supporting PWM generation, measurement of duty cycle and period of input PWM
wave, measurement of the time of set PWM wave numbers and tailwind/headwind detection (RSD)
➢ Timer3/Timer4: Timers supporting PWM generation, and measurement of duty cycle and period
of input PWM wave.
➢ Systick Timer
➢ RTC
◼ Communication interfaces:
➢ 1 SPI
➢ 1 I2C
➢ 2 UARTs and UART2 supports LIN slave mode
◼ Dual-channel DMA, supporting I2C, SPI, UART
◼ Analog peripherals:
➢ 12-bit ADC, operating with 1μs conversion time and internal VREF or external VREF
selectable as reference voltage
➢ Number of ADC channels:
◆ PU6332N: 8
➢ Built-in VREF, with 3V, 4V, 4.5V or VDD5 as the internal reference
➢ Built-in VHALF with VREF/2 as the internal reference
➢ 3 standalone operational amplifiers, where PGA is configurable for AMP0
➢ 3-channel analog comparator
➢ DAC: Single-channel 9-bit, single-channel 6-bit
◼ Built-in MOSFET driver
3P3N pre-driver
◼ FOC module supports single/dual/triple-shunt current sampling
◼ Built-in oscillator:
➢ 24MHz ±2
- Package
-
QFN40
- Datasheet
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