PU6832N
- Description
- The high-performance motor drive chip incorporates ME core and 8051 core. ME core integrates FOC, MDU, LPF, PID and SVPWM modules which allow for automatic calculation of FOC or square wave control by hardware used for sensored/sensorless BLDC/PMSM motors. 8051 core is used for parameter configuration and routine processing. Most of 8051 core instruction cycle takes 1 or 2 clock cycle(s). The dual cores work in parallel to achieve high-performance motor control. The chip integrates high-speed operational amplifiers, comparators, pre-driver, high-speed ADC, CRC, SPI, I2C, UART, LIN, Timers and high-speed LDO module, which are essential for FOC or square wave control based BLDC/PMSM motors.
Package of PU6832N is QFN32.
- Features
-
◼ Power supply:
➢ High-voltage single-power supply mode: When VCC_MODE = 0, external power supply 5V~28V
is connected to VCC pin, and internal LDO supplies VDD5 voltage.
➢ Low-voltage single-power supply mode: When VCC_MODE = 1, external power supply
3V~5.5V is connected to VDD5 pin, and VDD5 pin is shorted to VCC pin.
➢ Dual-power supply mode: When VCC_MODE = 1, external power supply 1 (5V~36V) is
connected to VCC pin, and external power supply 2 (5V) is connected to VDD5 pin.
◼ Dual core: 8051 core and ME core
◼ An instruction cycle mostly takes 1 or 2 system clock cycle(s)
◼ 16kB Flash ROM with CRC, self-program and code protection
◼ 256 bytes IRAM and 768 bytes XRAM
◼ ME: Core integrating PID module, FOC module, MDU auxiliary computing module and LPF module
◼ 16 interrupt sources with 4 configurable priority levels
◼ Number of GPIOs:
➢ PU6832N: 22
◼ Timer:
➢ Timer1: Timer designed forsquare wave motor drive, supporting square wave drive timing control,
automatic commutation, cycle-by-cycle current limiting and Hall/BEMF-based position sensing
➢ Timer2: Timer supporting PWM output, measurement of duty cycle and period of input PWM
wave, measurement of the time of set PWM wave numbers, QEP decoding, tailwind/headwind
detection (RSD), rotation direction and speed detection of step motor
➢ Timer3/Timer4: Timers supporting PWM output, and measurement of duty cycle and period of
input PWM wave. Timer4 supports FG generation and Timer3 supports up to 48MHz input.
➢ Systick Timer
➢ RTC
◼ Communication interface:
➢ 1*SPI
➢ 1*I
2C
➢ 2*UARTs, supporting single-wire mode
➢ 1*LIN
➢ Dual-channel DMA, supporting data transmission via I
2C/SPI/ UART/LIN
◼ Analogue peripherals:
➢ 12-bit ADC, operating with 1μs conversion time and internal VREF or external VREF selectable
as reference voltage
➢ Number of ADC channels:
◆ PU6832N: 11
➢ Internal VREF (VDD5) as internal reference
➢ Internal VHALF (VREF/2) can be selected as internal reference
➢ 3 standalone operational amplifiers, where the gain of AMP0 is configurable
➢ 3-channel analog comparators
➢ DAC: Single-channel 9-bit, single-channel 6-bit
◼ Built-in 3P3N pre-driver
◼ FOC module supports single/dual/triple-shunt current sampling
◼ Built-in oscillator:
➢ 24MHz fast RC oscillator
➢ 32.8kHz slow RC oscillator
◼ WDT
◼ LVD
◼ TSD
◼ Two-wire FICE protocol based in-circuit emulation
- Package
-
QFN32
- Datasheet
-
Download
