PU6861N
- Description
- The high-performance motor drive chip incorporates ME core and 8051 core. ME core implements motor control in real time. 8051 core is used for parameter configuration and routine processing. Most of 8051 core instruction cycle takes 1T or 2T clock cycle(s). The dual cores work in parallel to achieve high-performance motor control. The chip integrates high-speed operational amplifiers, comparators, high-speed ADC, multiplier/divider, CRC, SPI, I2C, UART, Timers, PWM modules and built-in high-voltage LDO, which are suitable for FOC or square-wave based BLDC/PMSM motors.
PU6861N supports 6N pre-driver output and its package is QFN40.
- Features
-
◼ Power supply:
➢ PU6861N: (Mode 1) VCC=5~24V, VDRV=7~18V
◼ Dual core: Motor engine ME and 8051 core. ME realizes FOC/BLDC control automatically by
hardware; 8051 core is used In parameter configuration and daily transaction processing
◼ An instruction cycle mostly takes 1 or 2 system clock cycle(s)
◼ 16KB Flash ROM, with CRC verification, support self-write and code protection
◼ 256 bytes IRAM and 768 bytes XRAM
◼ ME: Integrated LPF, proportional integrator (PI), BLDC module, FOC module
◼ 1T 16 x16 multiplier and 16T 32/16 divider
◼ 15 interrupt sources with 4 configurable priority levels
◼ Number of GPIOs:
➢ PU6861N: 19
◼ Timer:
➢ 2*Programmable timers with capture feature
➢ 1*QEP decoding programmable timer
➢ 1*BLDC motor dedicated timer
➢ 1*General-purpose timer
➢ 1*RTC
◼ Dual-channel DMA: supporting data transmission via I
2C/SPI/UART
◼ Analog peripherals:
➢ 12-bit ADC, operating with 0.9μs conversion time and internal VREF or external VREF
selectable as reference voltage
➢ Number of ADC channels:
◆ PU6861N: 9
➢ Internal VREF. 3V, 4V, 4.5V and VDD5 can be selected as the internal reference
➢ Internal VHALF, with 1/2 VREF as the internal reference
➢ 1*Independent operational amplifiers
➢ 3-channel analog comparator
➢ 8-bit DAC
◼ Driver type:
➢ 6N Pre-driver
◼ Automatic commutation, cycle-by-cycle current limiting and Hall/BEMF-based position sensing
for BLDC motor control
◼ FOC driver supports single-shunt current sampling
◼ FOC driver supports overmodulation
◼ Clock Source
Internal fast-speed clock 24MHz±2%
◼ WDT
◼ Two-wire FICE protocol based in-circuit emulation
- Package
-
QFN40
- Datasheet
-
Download
